This invention relates generally to processor input/output (I/O) interfacing within a computing environment, and more particularly to scalable adapter level error detection, isolation, and reporting.
In enterprise class servers, there is a need to protect the integrity of data generated by adapters. There is also a need to provide isolation and reporting when errors are detected for these adapters. Typical solutions are either primitive, provide no isolation, do not protect the data or are complex and not scalable. This invention provides a robust, scalable solution that is simple to implement in hardware and/or software. Protocols, such as PCIe, that do not acknowledge certain operations (e.g. DMA Writes), leave data integrity exposures in the event of errors. Current systems either ignore the error or require complex hardware modifications in order to properly capture error conditions.